(1) Field of the Invention
The present invention relates to a semiconductor memory device in which memory cells are periodically read, sensed and re-written to an activated level, as well as to a refresh address signal generating method for use in the semiconductor memory device during the refresh operation.
(2) Description of the Related Art
Dynamic random access memories (DRAM), such as those comprised of metal oxide semiconductor field effect transistors (MOSFET), are widely used in various computers and portable electronic systems. Typically, as for a DRAM, an array of memory cells is fabricated on a single integrated circuit chip, each of the memory cells including an access transistor and a storage capacitor.
In a one-device DRAM memory cell, the value of the memory bit is represented by a voltage stored on the cell's capacitor. This voltage is written into the storage capacitor by asserting the word line such that the transistor is turned ON. The desired data state is then imposed on the bit line. Typically, this will be either 5V to represent a "1" or 0V to represent a "0". Since the transistor is ON, this voltage will be transferred onto the capacitor. Next, the word line voltage is returned to a low voltage, which turns the transistor OFF, isolating the charge on the capacitor.
To read the information from the memory cell described above, the word line is again asserted after the bit line has been connected to the input of a sense amplifier circuit. The charge from the capacitor is then transferred to the sense amplifier, where it can be detected as a "1" or a "0". This readout procedure is destructive, since it disturbs the information in the storage capacitor. Hence, the read operation must be followed by a subsequent write operation. Charge stored on the memory cell's capacitor does not remain on the capacitor indefinitely. Due to a variety of leakage paths, the charge eventually leak, off the capacitor, causing the memory cell to loose its information. To alleviate this problem, each memory cell in the DRAM must be periodically read, sensed, and re-written to a full level. Hereinafter, this periodical read/write procedure for the DRAM will be called the refresh operation.
To provide high packing density of the cells in the DRAM and to allow hierarchical addressing, the memory cells are physically configured in a square or rectangular array on the integrated circuit chip. A single bit line is shared by many memory cells. Also, a single word line is shared by many memory cells. By running the word and bit lines in orthogonal directions, only one memory cell shares the combination of a given word and bit line. This orthogonal configuration of control lines allows a two-level hierarchical addressing scheme. One level selects a single word line (which is called a row). The second addressing level selects a single bit line (which is called a column). Theoretically, a 4M DRAM array could be constructed of 2K word lines and 2K bit lines.
To refresh the memory cell array in the DRAM, one simply selects a word line, activates the sense amplifiers, and deselects the word lines. This must be repeated for all word lines in the chip at least once every refresh cycle. Generally, it is necessary to always start a subsequent refresh operation from the memory cell which was first refreshed during the previous refresh cycle, and to sequentially increment the address of the memory cell to be refreshed, in order to keep all the memory cells of the chip at the activated levels.
FIG. 1 is a time chart for explaining the above-mentioned refresh operation of the DRAM. For the sake of simplicity of description, suppose that a 3-bit refresh address signal is used to indicate a specific location of the memory cell to be refreshed in the memory device.
In FIG. 1, (A) indicates a bit signal A0 having a first high/low-state change period T1, (B) indicates a bit signal A1 having a second high/low-state change period T2 which is twice the period T1, and (C) indicates a bit signal A2 having a third high/low-state change period T3 which is four times the period T1. These bit signals A2, A1 and A0 constitute the 3-bit refresh address signal (A2,A1,A0).
In a case of the refresh operation of FIG. 1, the refresh operation is started from the memory cell at (0,0,0) and the address of the memory cell to be refreshed is incremented in the sequence of (0,0,0), (0,0,1), (0,1,0), . . . , (1,1,1), so as to refresh all the memory cells of the semiconductor memory device once every refresh cycle. Hence, a subsequent refresh operation is always started from the memory cell which was first refreshed during the previous refresh cycle, and the address of the memory cell to be refreshed is sequentially incremented.
However, in the case of the refresh operation of FIG. 1, the variations of the capacitive load of the memory device at different memory addresses are not taken into account. The bit signals A2, A1 and A0 are assigned for the refresh address signal in a fixed manner, and the address of the memory cell to be refreshed in the memory device is sequentially incremented with the refresh address signal. If the capacitive load of the memory device at the address of the first memory cell (or at (0,0,0) in the above case) from which the refresh operation is started is the largest, the power consumption required for the DRAM during the refresh operation will be significantly increased. The power consumption of the DRAM affects the overall system density or portability of the overall memory system. Due to a large number of storage elements in a main memory system, if a significant power is used by each individual memory cell, a special cooling mechanism will be required to remove the heat from the system. This increases the cost and reduces the density of the overall system.